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EMIF02-MIC02F2
2-line IPADTM, EMI filter and ESD protection
Features

EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering Lead free package Very low PCB space consuming: 1.42 mm x 0.92 mm Very thin package: 0.65 mm High efficiency in ESD suppression High reliability offered by monolithic integration High reducing of parasitic elements through integration and wafer level packaging Figure 1. Pin configuration (bump side)
3 2 1
Flip Chip (6 bumps)
Complies with the following standards
I2
GND
I1
A
IEC 61000-4-2 level 4 on input pins - 15 kV (air discharge) - 8 kV (contact discharge) IEC 61000-4-2 level 1 on input pins - 2 kV (air discharge) - 2 kV (contact discharge)
O2
GND
O1
B
Figure 2.
Basic cell configuration
Applications
Where EMI filtering in ESD sensitive equipment is required:

Input
Low-pass Filter Output Ri/o = 470 W Cline = 16 pF
Mobile phones and communication systems Computers, printers and MCU Boards
GND GND GND
Description
The EMIF02-MIC02 is a highly integrated devices designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interferences. The EMIF02 Flip Chip packaging means the package size is equal to the die size. This filter includes an ESD protection circuitry which prevents the device from destruction when subjected to ESD surges up 15 kV.
TM: IPAD is a trademark of STMicroelectronics.
April 2008
Rev 3
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Electrical characteristics
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EMIF02-MIC02F2
1
Electrical characteristics
Table 1.
Symbol Tj Top Tstg
Absolute ratings (Tamb = 25 C)
Parameter junction temperature Operating temperature range Storage temperature range Value 125 -40 to +85 -55 to 150 Unit C C C
Table 2.
Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Symbol VBR IRM RI/O Cline
Electrical characteristics (Tamb = 25 C)
Parameters Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Series resistance between input and output Input capacitance per line Test conditions IR = 1 mA VRM = 12 V per line 423 @0V 470 40 Min 14 Typ 16 500 517 45 Max Unit V nA pF
IPP VCL VBR VRM IR IRM IRM IR VRM VBR VCL V I IPP
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EMIF02-MIC02F2
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Figure 3.
- 10.00 dB - 15.00 - 20.00 - 25.00 - 30.00 - 35.00
S21 (dB) attenuation measurement Figure 4. and Aplac simulation
-20.00 dB -30.00
Measurement
Analog crosstalk measurements
-40.00
I2/O1
-50.00
-60.00
- 40.00 - 45.00
Simulation
-70.00
- 50.00 1.0M
3.0M
10.0M
30.0M
100.0M 300.0M f/Hz
1.0G
3.0G
-80.00 1.0M
3.0M
10.0M
30.0M
100.0M f/Hz
300.0M
1.0G
3.0G
Figure 5.
Digital crosstalk measurement
Figure 6.
ESD response to IEC61000-4-2 (-15 kV air discharge) on one input V(in) and on one output (Vout)
Figure 7.
ESD response to IEC61000-4-2 (+15 kV air discharge) on one input V(in) and on one output (Vout)
Figure 8.
Line capacitance versus applied voltage
C(pF) 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 11 12 VR(V)
F=1MHz Vosc=30mVRMS Tj=25C
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Application information
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EMIF02-MIC02F2
2
Application information
Figure 9.
I1
Aplac model
R_470R O1
gnd
Cox
MODEL = D01-int MODEL = D01-ext
Cox
50pH
Rsubump MODEL = D01-gnd gnd
50pH
Rsubump
50m
50m
Rsubump MODEL = D01-ext Cox MODEL = D01-int
Rsubump
Lgnd Cgnd Cgnd Rgnd
O2
Lgnd
Cox
Rgnd
I2 R_470R
Figure 10. Aplac parameters
Model D01-ext BV = 7 CJO = Cz_ext IBV = 1u IKF = 1000 IS = 10f ISR = 100p N=1 M = 0.3333 RS = Rs_ext VJ = 0.6 TT = 50n Model D01-int BV = 7 CJO = Cz_int IBV = 1u IKF = 1000 IS = 10f ISR = 100p N=1 M = 0.3333 RS = Rs_int VJ = 0.6 TT = 50n Model D01-gnd BV = 7 CJO = Cz_gnd IBV = 1u IKF = 1000 IS = 10f ISR = 100p N=1 M = 0.3333 RS = Rs_gnd VJ = 0.6 TT = 50n
Ls 400pH Rs 100m R_470R 482.6 Cz_ext 8.73pF Rs_ext 850m Cz_int 2.9pF Rs_int 850m Cz_gnd 215.61pF Rs_gnd 470m Rgnd 10m Lgnd 48pH Cgnd 0.15pF Cox 3.05pF Rsubump 200m
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EMIF02-MIC02F2
www..com Ordering information scheme
3
Ordering information scheme
Figure 11. Ordering information scheme
EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10 pF or 3 letters = application 2 digits = version Package F = Flip Chip x = 2: Lead-free, pitch = 500 m, bump = 315 m
yy
-
xxx zz
Fx
4
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 12. Package dimensions
500 m 50 315 m 50 650m 65
500 m 50
210 m
0.92 mm 50m
210 m
1.42 mm 50 m
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Ordering information
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EMIF02-MIC02F2
Figure 13. Footprint
Figure 14. Marking
Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)
Copper pad Diameter: 250 m recommended, 300 m max
Solder stencil opening: 330 m
E
Solder mask opening recommendation: 340 m min for 300 m copper pad diameter
xxz y ww
Dot identifying Pin A1 location 4 0.1 O 1.5 0.1
Figure 15. Flip Chip tape and reel specification
1.75 0.1 3.5 0.1
1.02
0.73 0.05
All dimensions in mm
8 0.3
STE
STE
STE
xxz yww
User direction of unreeling
xxz yww
xxz yww
4 0.1
1.47
5
Ordering information
Table 3. Ordering information
Marking FJ Package Flip Chip Weight 2.3 mg Base qty 5000 Delivery mode Tape and reel 7"
Order code EMIF02-MIC02F2
Note:
More information is available in the application notes: AN1235:"Flip Chip: Package description and recommendations for use" AN1751: "EMI filters: Recommendations and measurements"
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EMIF02-MIC02F2
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Revision history
6
Revision history
Table 4.
Date 12-Oct-2004 11-Jan-2006 17-Apr-2008
Document revision history
Revision 1 2 3 Initial release. ECOPACK statement added. Die dimensions modified in Figure 12. and first page. Typographical errors corrected. Updated ECOPACK statement. Updated Figure 11, Figure 12 and Figure 15. Reformatted to current standards. Changes
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EMIF02-MIC02F2
Please Read Carefully:
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